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87972dyi www.idt.com rev. e june 25, 2010 1 ICS87972I l ow s kew , 1- to -12 lvcmos/lvttl c lock m ultiplier /z ero d elay b uffer p in a ssignment g eneral d escription the ICS87972I is a low skew, lvcmos/lvttl clock generator. the ICS87972I has three selectable inputs and provides fourteen lvcmos/lvttl outputs. the ICS87972I is a highly flexible device. using the crystal oscillator input, it can be used to generate clocks for a system. all of these clocks can be the same frequency or the device can be configured to generate up to three different frequencies among the three output banks. using one of the single ended inputs, the ICS87972I can be used as a zero delay buffer/multiplier/divider in clock distribution applications. the three output banks and feedback output each have their own output dividers which allows the device to generate a multitude of different bank frequency ratios and output-to- input frequency ratios. in addition, 2 outputs in bank c (qc2, qc3) can be selected to be inverting or non-inverting. the output frequency range is 8.33 mhz to125mhz. input frequency range is 5mhz to 120mhz. the ICS87972I also has a qsync output which can be used for system synchronization purposes. it monitors bank a and bank c outputs and goes low one period of the faster clock prior to coincident rising edges of bank a and bank c clocks. qsync then goes high again when the coincident rising edges of bank a and bank c occur. this feature is used primarily in applications where bank a and bank c are running at different frequencies, and is particularly useful when they are running at non-integer multiples of one another. example applications: 1. system clock generator: use a 16.66mhz crystal to generate eight 33.33mhz copies for pci and four 100mhz copies for the cpu or pci-x. 2. line card multiplier: multiply 19.44mhz from a back plane to 77.76mhz for the line card asics and serdes. 3. zero delay buffer for synchronous memory: fan out up to twelve 100mhz copies from a memory controller ref- erence clock to the memory chips on a memory module with zero delay. f eatures ? fully integrated pll ? fourteen lvcmos/lvttl outputs; (12) clocks, (1) feedback, (1) sync ? selectable crystal oscillator interface or lvcmos/lvttl reference clock inputs ? clk0, clk1 can accept the following input levels: lvcmos or lvttl ? output frequency range: 8.33mhz to 125mhz ? vco range: 200mhz to 480mhz ? output skew: 550ps (maximum) ? cycle-to-cycle jitter: 100ps (typical) ? full 3.3v supply voltage ? -40c to 85c ambient operating temperature ? available in both standard andd lead-free rohs-compliant packages ? compatible with power pc? and p entium? microprocessors fsel_fb0 v dd qfb gndo ext_fb qb3 v ddo qb2 gndo qb1 v ddo qb0 gndo 40 41 42 43 44 45 46 47 48 49 50 51 52 1 2 3 4 5 6 7 8 9 10 11 12 13 26 25 24 23 22 21 20 19 18 17 16 15 14 39 38 37 36 35 34 33 32 31 30 29 28 27 fsel_b1 fsel_b0 fsel_a1 fsel_a0 qa3 v ddo qa2 gndo qa1 v ddo qa0 gndo vco_sel fsel_fb1 qsync gndo qc0 v ddo qc1 fsel_c0 fsel_c1 qc2 v ddo qc3 gndo inv_clk v dda xtal2 xtal1 clk1 clk0 clk_sel ref_sel pll_sel fsel_fb2 frz_data frz_clk nmr/oe gndi 52-lead lqfp 10mm x 10mm x 1.4mm package body y package top view ICS87972I
87972dyi www.idt.com rev. e june 25, 2010 2 ICS87972I l ow s kew , 1- to -12 lvcmos/lvttl c lock m ultiplier /z ero d elay b uffer sync frz sync frz sync frz sync frz sync frz sync frz sync frz sync frz sync frz sync frz sync frz sync frz xtal1 xtal2 vco_sel pll_sel ref_sel clk0 clk1 clk_sel ext_fb fsel_fb2 nmr/oe fsel_a0:1 fsel_b0:1 fsel_c0:1 fsel_fb0:2 frz_clk frz_data inv_clk qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qc0 qc1 qc2 qc3 qfb qsync output disable circuitry data generator 12 2 2 2 3 sync pulse 4, 6, 8, 12 4, 6, 8, 10 2, 4, 6, 8 2 0 1 0 1 0 1 power-on reset phase detector vco lpf dq dq dq dq dq dq b lock d iagram 1 0 4, 6, 8, 10
87972dyi www.idt.com rev. e june 25, 2010 3 ICS87972I l ow s kew , 1- to -12 lvcmos/lvttl c lock m ultiplier /z ero d elay b uffer qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qc0 qc1 qc2 qc3 qfb qsync xtal1 xtal2 clk0 clk1 clk_sel ref_sel ext_fb vco_sel pll_sel 0 1 1 0 0 1 1 2 sync frz sync frz sync frz sync frz sync frz sync frz sync frz sync frz sync frz sync frz sync frz o utput d isable c ircuitry 0 1 0 1 pll vco r ange 200mhz - 480mhz sync frz 3 2 2 2 inv_clk fsel_a[0:1] fsel_b[0:1] fsel_c[0:1] fsel_fb[0:2] 0 0 4 0 1 6 1 0 8 1 1 12 fsel_ a1 a0 qax 0 0 4 0 1 6 1 0 8 1 1 10 fsel_ b1 b0 qbx 0 0 0 4 0 0 1 6 0 1 0 8 0 1 1 10 1 0 0 8 1 0 1 12 1 1 0 16 1 1 1 20 fsel_ fb2 fb1 fb0 qfb 0 0 2 0 1 4 1 0 6 1 1 8 fsel_ c1 c0 qcx nmr/oe s implified b lock d iagram frz_clk frz_data
87972dyi www.idt.com rev. e june 25, 2010 4 ICS87972I l ow s kew , 1- to -12 lvcmos/lvttl c lock m ultiplier /z ero d elay b uffer t able 1. p in d escriptions r e b m u ne m a ne p y tn o i t p i r c s e d 1i d n gr e w o p. d n u o r g y l p p u s r e w o p 2e o / r m nt u p n ip u l l u p c i g o l n e h w . e l b a n e t u p t u o w o l e v i t c a . t e s e r r e t s a m h g i h e v i t c a h g i h n i e r a s t u p t u o e h t d n a t e s e r e r a s r e d i v i d l a n r e t n i e h t , h g i h s t u p t u o e h t d n a s r e d i v i d l a n r e t n i e h t , w o l c i g o l n e h w . ) z - i h ( e c n a d e p m i . s l e v e l e c a f r e t n i l t t v l / s o m c v l . d e l b a n e e r a 3k l c _ z r ft u p n ip u l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . y r t i u c r i c e z e e r f r o f t u p n i k c o l c 4a t a d _ z r ft u p n ip u l l u p . y r t i u c r i c e z e e r f r o f t u p n i a t a d n o i t a r u g i f n o c . s l e v e l e c a f r e t n i l t t v l / s o m c v l 7 2 , 6 2 , 5 , 2 b f _ l e s f , 1 b f _ l e s f 0 b f _ l e s f t u p n ip u l l u p . e u l a v e d i v i d k c a b d e e f l o r t n o c s n i p t c e l e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l 6l e s _ l l pt u p n ip u l l u p t u p t u o e h t o t t u p n i e h t s a s k c o l c e c n e r e f e r d n a l l p e h t n e e w t e b s t c e l e s d n a l l p e h t s e s s a p y b , w o l n e h w . l l p s t c e l e s , h g i h n e h w . s r e d i v i d . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s k c o l c e c n e r e f e r 7l e s _ f e rt u p n ip u l l u p s t c e l e s , w o l n e h w . k c o l c e c n e r e f e r d n a l a t s y r c n e e w t e b s t c e l e s . s t u p n i l a t s y r c s t c e l e s , h g i h n e h w . 1 k l c r o 0 k l c . s l e v e l e c a f r e t n i l t t v l / s o m c v l 8l e s _ k l ct u p n ip u l l u p . 0 k l c s t c e l e s , w o l n e h w . t u p n i t c e l e s k c o l c . s l e v e l e c a f r e t n i l t t v l / s o m c v l . 1 k l c s t c e l e s , h g i h n e h w 0 1 , 91 k l c , 0 k l ct u p n ip u l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . s t u p n i k c o l c e c n e r e f e r 2 1 , 1 1 , 1 l a t x 2 l a t x t u p n i . t u p t u o e h t s i 2 l a t x . t u p n i e h t s i 1 l a t x . e c a f r e t n i r o t a l l i c s o l a t s y r c 3 1v a d d r e w o p. n i p y l p p u s g o l a n a 4 1k l c _ v n it u p n ip u l l u p . s t u p t u o 3 c q d n a 2 c q r o f t c e l e s k c o l c d e t r e v n i . s l e v e l e c a f r e t n i l t t v l / s o m c v l , 0 3 , 4 2 , 5 1 1 5 , 7 4 , 9 3 , 5 3 o d n gr e w o p. d n u o r g y l p p u s r e w o p 3 2 , 1 2 , 8 1 , 6 1 , 2 c q , 3 c q 0 c q , 1 c q t u p t u o 7 . s t u p t u o k c o l c c k n a b . e c n a d e p m i t u p t u o l a c i p y t . s l e v e l e c a f r e t n i l t t v l / s o m c v l 3 3 , 2 2 , 7 1 9 4 , 5 4 , 7 3 v o d d r e w o p. s n i p y l p p u s t u p t u o 0 2 , 9 1 , 1 c _ l e s f 0 c _ l e s f t u p n ip u l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . s t u p t u o c k n a b r o f s n i p t c e l e s 5 2c n y s qt u p t u o , 1 e r u g i f o t r e f e r . c k n a b d n a a k n a b r o f t u p t u o n o i t a z i n o r h c n y s . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s m a r g a i d g n i m i t 8 2v d d r e w o p. s n i p y l p p u s e r o c 9 2b f qt u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p t u o k c o l c k c a b d e e f 1 3b f _ t x et u p n ip u l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . k c a b d e e f l a n r e t x e 8 3 , 6 3 , 4 3 , 2 3 , 2 b q , 3 b q 0 b q , 1 b q t u p t u o 7 . s t u p t u o k c o l c b k n a b . e c n a d e p m i t u p t u o l a c i p y t . s l e v e l e c a f r e t n i l t t v l / s o m c v l 1 4 , 0 4 , 1 b _ l e s f 0 b _ l e s f t u p n ip u l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . s t u p t u o b k n a b r o f s n i p t c e l e s 3 4 , 2 4 , 1 a _ l e s f 0 a _ l e s f t u p n ip u l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . s t u p t u o a k n a b r o f s n i p t c e l e s 0 5 , 8 4 , 6 4 , 4 4 , 2 a q , 3 a q 0 a q , 1 a q t u p t u o 7 . s t u p t u o k c o l c a k n a b . e c n a d e p m i t u p t u o l a c i p y t . s l e v e l e c a f r e t n i l t t v l / s o m c v l 2 5l e s _ o c vt u p n ip u l l u p s t c e l e s , w o l n e h w . 1 o c v s t c e l e s , h g i h n e h w . o c v s t c e l e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l . 2 o c v : e t o n p u l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t s r e f e r
87972dyi www.idt.com rev. e june 25, 2010 5 ICS87972I l ow s kew , 1- to -12 lvcmos/lvttl c lock m ultiplier /z ero d elay b uffer t able 2. p in c haracteristics t able 3a. o utput b ank c onfiguration s elect f unction t able s t u p n is t u p t u os t u p n is t u p t u os t u p n is t u p t u o 1 a _ l e s f0 a _ l e s fa q1 b _ l e s f0 b _ l e s fb q1 c _ l e s f0 c _ l e s fc q 00 4 00 4 002 01 6 016 014 10 8 108 106 11 2 1 110 1 118 t able 3b. f eedback c onfiguration s elect f unction t able s t u p n is t u p t u o 2 b f _ l e s f1 b f _ l e s f0 b f _ l e s fb f q 000 4 00 1 6 010 8 011 0 1 10 0 8 10 1 2 1 110 6 1 111 0 2 t able 3c. c ontrol i nput s elect f unction t able n i p l o r t n o c0 c i g o l1 c i g o l l e s _ o c v2 / o c vo c v l e s _ f e r1 k l c r o 0 k l cl a t x l e s _ k l c0 k l c1 k l c l e s _ l l pl l p s s a p y bl l p e l b a n e e o / r m nz i h t u p t u o / t e s e r r e t s a ms t u p t u o e l b a n e k l c _ v n i3 c q , 2 c q d e t r e v n i - n o n3 c q , 2 c q d e t r e v n i l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k c d p e c n a t i c a p a c n o i t a p i s s i d r e w o p ) t u p t u o r e p ( v a d d v , d d v , o d d v 5 6 4 . 3 =8 1f p r t u o e c n a d e p m i t u p t u o572 1
87972dyi www.idt.com rev. e june 25, 2010 6 ICS87972I l ow s kew , 1- to -12 lvcmos/lvttl c lock m ultiplier /z ero d elay b uffer fvco qa qc qsync qa qc qsync qc(2) qa(4) qsync qc(2) qa(8) qsync qc(2) qa(8) qsync qa(6) qc(8) qsync qa(12) qc(2) qsync f igure 1. t iming d iagrams 1:1 m ode 2:1 m ode 3:1 m ode 3:2 m ode 4:1 m ode 4:3 m ode 6:1 m ode
87972dyi www.idt.com rev. e june 25, 2010 7 ICS87972I l ow s kew , 1- to -12 lvcmos/lvttl c lock m ultiplier /z ero d elay b uffer t able 4a. p ower s upply dc c haracteristics , v dd = v dda = v ddo = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a d d e g a t l o v y l p p u s g o l a n a 5 3 9 . 23 . 35 6 4 . 3v v o d d e g a t l o v y l p p u s t u p t u o 5 3 1 . 33 . 35 6 4 . 3v i d d t n e r r u c y l p p u s r e w o ps n i p r e w o p l l a0 5 2a m i a d d t n e r r u c y l p p u s g o l a n a 0 2a m . s n o i t a r u g i f n o c e m o s n i d e r i u q e r e b y a m g n i l d n a h l a m r e h t l a i c e p s : e t o n t able 4b. lvcmos/lvttl dc c haracteristics , v dd = v dda = v ddo = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 26 . 3v v l i e g a t l o v w o l t u p n i 8 . 0v i n i t n e r r u c t u p n i 0 2 1 a v h o e g a t l o v h g i h t u p t u oi h o a m 0 2 - =4 . 2v v l o e g a t l o v w o l t u p t u oi l o a m 0 2 =5 . 0v a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5 v outputs, v o -0.5v to v ddo + 0.5v package thermal impedance, ja 42.3c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. t able 5. i nput f requency c haracteristics , v dd = v dda = v ddo = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f n i y c n e u q e r f t u p n i 1 e t o n ; 1 k l c , 0 k l c 0 2 1z h m 2 l a t x , 1 l a t x0 15 2z h m k l c _ z r f 0 2z h m f o e g n a r o c v e h t n i s i " e d i v i d k c a b d e e f * k c o l c " e r u s n e o t o i t a r e d i v i d k c a b d e e f e h t n o s d n e p e d y c n e u q e r f t u p n i : 1 e t o n . z h m 0 8 4 o t z h m 0 0 2
87972dyi www.idt.com rev. e june 25, 2010 8 ICS87972I l ow s kew , 1- to -12 lvcmos/lvttl c lock m ultiplier /z ero d elay b uffer t able 6. c rystal c haracteristics , v dd = v dda = v ddo = 3.3v5%, t a = -40c to 85c t able 7. ac c haracteristics , v dd = v dda = v ddo = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 2 5 2 1z h m 4 0 2 1z h m 6 0 8z h m 8 0 6z h m ) ? ( t ; t e s f f o e s a h p c i t a t s 1 e t o n 0 k l c b f q 8 z h m 0 5 = y c n e u q e r f n i 0 7 2 -0 3 10 3 5s p 1 k l c0 3 3 -0 70 7 4s p t ) o ( k s4 , 2 e t o n ; w e k s t u p t u o 0 5 5s p t ) c c ( t i j4 e t o n ; r e t t i j e l c y c - o t - e l c y c 0 0 1 s p f o c v e g n a r k c o l o c v l l p0 0 20 8 4z h m t k c o l 3 e t o n ; e m i t k c o l l l p 0 1s m t r t / f ; e m i t l l a f / e s i r t u p t u o e t o n3 v 2 o t v 8 . 05 1 . 02 . 1s n t w p h t d i w e s l u p t u p t u ot d o i r e p 0 5 7 - 2 /t d o i r e p 0 0 5 2 /t d o i r e p 0 5 7 + 2 /s p t l z p t , h z p 3 e t o n ; e m i t e l b a n e t u p t u o 0 1s n t z l p t , z h p 3 e t o n ; e m i t e l b a s i d t u p t u o 8s n l a n g i s t u p n i k c a b d e e f e g a r e v a e h t d n a k c o l c e c n e r e f e r t u p n i e h t n e e w t e b e c n e r e f f i d e m i t e h t s a d e n i f e d : 1 e t o n . e l b a t s s i y c n e u q e r f e c n e r e f e r t u p n i e h t d n a d e k c o l s i l l p e h t n e h w . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n v t a d e r u s a e m o d d . 2 / . n o i t c u d o r p n i d e t s e t t o n . n o i t a z i r e t c a r a h c y b d e e t n a r a u g e r a s r e t e m a r a p e s e h t : 3 e t o n . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 4 e t o n r e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a l l i c s o f o e d o m l a t n e m a d n u f y c n e u q e r f 0 15 2z h m ) r s e ( e c n a t s i s e r s e i r e s t n e l a v i u q e 0 5 e c n a t i c a p a c t n u h s 7f p l e v e l e v i r d 1w m
87972dyi www.idt.com rev. e june 25, 2010 9 ICS87972I l ow s kew , 1- to -12 lvcmos/lvttl c lock m ultiplier /z ero d elay b uffer p arameter m easurement i nformation c ycle - to -c ycle j itter 3.3v o utput l oad ac t est c ircuit scope qx lvcmos 1.65v5% -1.65v5% o utput s kew s tatic p hase o ffset o utput r ise /f all t ime t sk(o) v ddo 2 v ddo 2 qy qx o utput d uty c ycle /p ulse w idth /p eriod t pw t period v ddo 2 v ddo 2 v ddo 2 t pw t period odc = qa0:qa3, qb0:qb3, qc0:qc3, qsync, qfb qa0:qa3, qb0:qb3, qc0:qc3, qsync, qfb ? ? ? ? v ddo 2 v ddo 2 v ddo 2 t cycle n t cycle n+1 t jit(cc) = t cycle n ? t cycle n+1 1000 cycles clock outputs 0.5v 2.4v 2.4v 0.5v t r t f ? ? t (?) v dd 2 v dd 2 clk0, clk1 ext_fb (where t (?) is any random sample, and t (?) mean is the average of the sampled cycles measured on controlled edges) t (?) mean = static phase offset v dd , v dda , v ddo gnd
87972dyi www.idt.com rev. e june 25, 2010 10 ICS87972I l ow s kew , 1- to -12 lvcmos/lvttl c lock m ultiplier /z ero d elay b uffer frz latched frz clocked qx f reeze internal qx internal qx out frz_clk frz_data start bit qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qc1 qc2 qc3 qsync a pplication i nformation f igure 2a. f reeze d ata i nput p rotocol u sing t he o utput f reeze c ircuitry o verview to enable low power states within a system, each output of ICS87972I (except qc0 and qfb) can be individually frozen (stopped in the logic ?0? state) using a simple serial interface to a 12 bit shift register. a serial interface was chosen to elimi- nate the need for each output to have its own output enable pin, which would dramatically increase pin count and package cost. common sources in a system that can be used to drive the ICS87972I serial interface are fpga?s and asics. p rotocol the serial interface consists of two pins, frz_data (freeze data) and frz_clk (freeze clock). each of the outputs which can be frozen has its own freeze enable bit in the 12 bit shift register. the sequence is started by supplying a logic ?0? start bit followed by 12nrz freeze enable bits. the period of each frz_data bit equals the period of the frz_clk signal. the frz_data serial transmission should be timed so the ICS87972I can sample each frz_data bit with the rising edge of the frz_clk signal. to place an output in the freeze state, a logic ?0? must be written to the respective freeze enable bit in the shift register. to unfreeze an output, a logic ?1? must be written to the respective freeze enable bit. outputs will not become enabled/ disabled until all 12 data bits are shifted into the shift register. when all 12 data bits are shifted in the register, the next rising edge of frz_clk will enable or disable the outputs. if the bit that is following the 12th bit in the register is a logic ?0?, it is used for the start bit of the next cycle; otherwise, the device will wait and won?t start the next cycle until it sees a logic ?0? bit. freez- ing and unfreezing of the output clock is synchronous (see the timing diagram below). when going into a frozen state, the out- put clock will go low at the time it would normally go low, and the freeze logic will keep the output low until unfrozen. likewise, when coming out of the frozen state, the output will go high only when it would normally go high. this logic, therefore, pre- vents runt pulses when going into and out of the frozen state. f igure 2b. o utput d isable t iming
87972dyi www.idt.com rev. e june 25, 2010 11 ICS87972I l ow s kew , 1- to -12 lvcmos/lvttl c lock m ultiplier /z ero d elay b uffer p ower s upply f iltering t echniques as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ICS87972I provides sepa- rate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd , v dda and v ddo should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 3 illustrates how a 10 resistor along with a 10 f and a .01 f bypass capacitor should be connected to each v dda pin. f igure 3. p ower s upply f iltering 10 v dda 10 f .01 f 3.3v .01 f v dd i nputs : c rystal i nput : for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k resistor can be tied from xtal_in to ground. clk i nput : for applications not requiring the use of a clock input, it can be left floating. though not required, but for additional protection, a 1k resistor can be tied from the clk input to ground. lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvcmos o utput : all unused lvcmos output can be left floating. we recommend that there is no trace attached.
87972dyi www.idt.com rev. e june 25, 2010 12 ICS87972I l ow s kew , 1- to -12 lvcmos/lvttl c lock m ultiplier /z ero d elay b uffer a pplication s chematic e xample figure 4 shows an application schematic example of ICS87972I. this example provides general handling of input/ output termination, logic control input and power supply filter- ing. in this example, the clock inputs are driven by lvcmos drivers. series termination for lvcmos drivers is shown. ad- ditional lvcmos termination approaches are shown in the lvcmos termination application note. the logic control in- r11 33 r2 43 zo = 50 r10 33 rd2 1k (u1-17) (u1-33) vdd r9 33 vdd=3.3v r5 1k rd1 not install ru1 1k c7 0.1uf r2 43 r1 43 (u1-37) zo = 50 logic input pin examples u1 87972i 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 39 38 37 36 35 34 33 32 31 30 29 28 27 52 51 50 49 48 47 46 45 44 43 42 41 40 gndi nmr/oe frz_clk frz_data fsel_fb2 pll_sel ref_sel clk_sel clk0 clk1 xtal 1 xtal 2 vdda inv_clk gndo qc3 vddo qc2 fsel_c1 fsel_c0 qc1 vddo qc0 gndo qsync fsel_fb1 gndo qb0 vddo qb1 gndo qb2 vddo qb3 ext_fb gndo qfb vdd fsel_fb0 vco_sel gndo qa0 vddo qa1 gndo qa2 vddo qa3 fsel_a0 fsel_a1 fsel_b0 fsel_b1 zo = 50 c6 0.1uf ro=16 ohm lvcmos (u1-45) vdd zo = 50 to logic input pins r12 33 lvcmos ro=16 ohm lvcmos r8 1k set logic input to '0' vdd c11 0.01u vddo=3.3v lvcmos zo = 50 r13 1k r3 43 c8 0.1uf r14 1k r7 10 - 15 zo = 50 vdd c3 0.1uf c4 0.1uf (u1-49) c5 0.1uf to logic input pins ro=16 ohm lvcmos ru2 not install vddo ro=16 ohm lvcmos vddo (u1-22) vdd zo = 50 zo = 50 vdd set logic input to '1' c16 10u c9 0.1uf put can be either hardwired on the board or controlled by lvcmos drivers. in this example, both hardwired and lvcmos driver controlling the logic input are shown. for the power supply pins, it is recommended at least one decoupling capacitor per power pin. the decoupling capacitors should be placed as close to the power pins as possible. f igure 4. ICS87972I l ayout s chematic
87972dyi www.idt.com rev. e june 25, 2010 13 ICS87972I l ow s kew , 1- to -12 lvcmos/lvttl c lock m ultiplier /z ero d elay b uffer r eliability i nformation t ransistor c ount the transistor count for ICS87972I is: 8364 t able 8. ja vs . a ir f low t able for 52 l ead lqfp ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 58.0c/w 47.1c/w 42. 0c/w multi-layer pcb, jedec standard test boards 42.3c/w 36.4c/w 34. 0c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
87972dyi www.idt.com rev. e june 25, 2010 14 ICS87972I l ow s kew , 1- to -12 lvcmos/lvttl c lock m ultiplier /z ero d elay b uffer t able 9. p ackage d imensions reference document: jedec publication 95, ms-026 p ackage o utline - y s uffix for 52 l ead lqfp n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s c c b m u m i n i ml a n i m o nm u m i x a m n 2 5 a - -- -0 6 . 1 1 a 5 0 . 0- -5 1 . 0 2 a 5 3 . 10 4 . 15 4 . 1 b 2 2 . 02 3 . 08 3 . 0 1 b 2 2 . 00 3 . 03 3 . 0 d c i s a b 0 0 . 2 1 1 d c i s a b 0 0 . 0 1 e c i s a b 0 0 . 2 1 1 e c i s a b 0 0 . 0 1 e c i s a b 5 6 . 0 c c c 5 4 . 0- -0 1 . 0 d d d - -- -3 1 . 0
87972dyi www.idt.com rev. e june 25, 2010 15 ICS87972I l ow s kew , 1- to -12 lvcmos/lvttl c lock m ultiplier /z ero d elay b uffer t able 10. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated device technology, inc. ( idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are impl ied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability, or other extraordinary environmental requirement s are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use i n life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t i y d 2 7 9 7 8i y d 2 7 9 7 8 s c ip f q l d a e l 2 5y a r tc 5 8 o t c 0 4 - t i y d 2 7 9 7 8i y d 2 7 9 7 8 s c ip f q l d a e l 2 5l e e r & e p a t 0 0 5c 5 8 o t c 0 4 - f l i y d 2 7 9 7 8f l i y d 2 7 9 7 8 s c ip f q l " e e r f - d a e l " d a e l 2 5y a r tc 5 8 o t c 0 4 - t f l i y d 2 7 9 7 8f l i y d 2 7 9 7 8 s c ip f q l " e e r f - d a e l " d a e l 2 5l e e r & e p a t 0 0 5c 5 8 o t c 0 4 - . t n i a l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
87972dyi www.idt.com rev. e june 25, 2010 16 ICS87972I l ow s kew , 1- to -12 lvcmos/lvttl c lock m ultiplier /z ero d elay b uffer t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d a1 4 . 1 2 d n a 0 2 s n i p d e d d a - e l b a t n o i t p i r c s e d n i p 2 0 / 9 / 9 a2 . r o t a r e n e g a t a d e h t o t s r e d i v i d g n i s s i m d e d d a - m a r g a i d k c o l b 2 0 / 8 1 / 0 1 a2 1. m a r g a i d e n i l t u o e g a k c a p d e s i v e r 2 0 / 5 / 2 1 b 2 t a 4 t 5 7 1 1 c e h t d e g n a h c - s c i t s i r e t c a r a h c n i p d p . x a m f p 8 1 o t l a c i p y t f p 5 2 m o r f t i m i l i e h t d e g n a h c - e l b a t y l p p u s r e w o p d d . x a m a m 0 5 2 o t . x a m a m 5 1 2 m o r f t i m i l : n o i t a m r o f n i n o i t a c i l p p a . " s e u q i n h c e t g n i r e t l i f y l p p u s r e w o p " , n o i t c e s d e d d a 3 0 / 4 2 / 3 b 2 t5 0 1 c d e g n a h c - s c i t s i r e t c a r a h c n i p n i . l a c i p y t f p 4 o t . x a m f p 4 m o r f . a 2 e r u g i f n o g n i l e b a l a t a d e z e e r f d e t c e r r o c 3 0 / 8 / 5 c a 4 t 6 t 7 8 v m u m i n i m d e g n a h c - e l b a t y l p p u s r e w o p a d d . v 5 3 9 . 2 o t v 5 3 1 . 3 m o r f 0 8 m o r f r s e d e g n a h c - e l b a t l a t s y r c 0 5 o t . 3 0 / 7 2 / 6 c1 1. t u o y a l c i t a m e h c s d e d d a 4 0 / 8 2 / 2 1 d 2 t 6 t 0 1 t 1 5 8 1 1 5 1 . t e l l u b e e r f - d a e l d d a - n o i t c e s s e r u t a e f 5 d e d d a - e l b a t s c i t s i r e t c a r a h c n i p 2 1 d n a . n i m r o t x a m t u o . . l e v e l e v i r d d e d d a - e l b a t s c i t s i r e t c a r a h c l a t s y r c d e d d a . s n i p t u p t u o d n a t u p n i d e s u n u r o f s n o i t a d n e m m o c e r . e t o n d n a g n i k r a m , r e b m u n t r a p e e r f - d a e l d e d d a - e l b a t n o i t a m r o f n i g n i r e d r o 5 0 / 9 2 / 1 1 c0 1 t5 1 7 1 . s c i m o r f t d i h t i w r e t o o f / r e d a e h s ' t e e h s a t a d d e t a d p u . n m u l o c r e b m u n r e d r o / t r a p m o r f x i f e r p " " s c i " " d e v o m e r . e g a p t c a t n o c d e d d a 0 1 / 5 2 / 6
87972dyi www.idt.com rev. e june 25, 2010 17 ICS87972I l ow s kew , 1- to -12 lvcmos/lvttl c lock m ultiplier /z ero d elay b uffer we?ve got your timing solution. sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 tech support netcom@idt.com 6024 silver creek valley road san jose, ca 95138 ? 2010 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names and marks are or m ay be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa

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